Services

Verification Services

Kacper Technology enables you to rapidly build verification environment helping to achieve your design and verification targets through its unique blend of innovative tools and technologies. Our verification methodology helps to build highly layered, scalable, reusable and extensible verification environments for module and SoC/ ASIC/ FPGA/ IP level verification, providing maximum functional coverage.

Our Capabilities:

   » Development of Verification Plan.

   » Development of reusable verification environment at module, chip or SoC level using Verification Methodologies like VMM       and OVM.

   » Development of Self-Checking Test Cases and Regression Suite.

   » Development of Assertion based Checkers and Protocol Monitors.

   » Functional and Code Coverage Analysis.

   » Test case execution and analysis.

   » Verification report generation.

   » Engineers at Kacper Technologies are equipped to provide proven and innovative solutions, to solve your verification
      needs.

Our Skill sets:

   » Hardware Verification Languages: System Verilog.

   » Verification Frameworks: VMM, VMM_LP and OVM.

   » Verification Technologies: Constrained Random Stimulus Generation, Assertion Based Verification and Coverage Driven       Verification and Low Power Verification.

   » Domain Knowledge: Ethernet/ 10Gb Ethernet, SONET/ SDH, Next generation SONET/ SDH, Automotive Protocols like       CAN and FlexRay.

   » Kacper Technology provides complete verification solutions right from test plan documentation to seeing the silicon       tape-out.

Our Deliverables:

   » Verification Plan.

   » Verification Report.

   » Test Benches and Test Suites.

   » Support Scripts.

   » Verification IP's.

Our Key Benefits:

   » Extensive design experience, knowledge of standards, portfolio of IPs and customer orientation help our customers bring       their product faster to the market.

   » Provides end to end verification assurance so that the customers can focus on more critical issues like product       conceptualization, architecture, features performance etc.

   » Enables accelerated verification of DUT with independently developed verification IP's.

   » Finds bugs faster there by reducing the rate of failure or re-spin.